Senior Wireline SerDes Design Engineer

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Reference:BH-2469

Sector:Electrical Engineering, Photonics / Opto

Salary:$150,000 to $300,000 Per Annum

Benefits:Bonus, 401K, Health Insurance + other benefits.

Town/City:San Jose

Contract Type:Permanent

Senior Wireline SerDes Design Engineer
Bay Area | $150,000–$300,000 + Bonus

A growing semiconductor company is developing next-generation connectivity solutions for AI datacentres, cloud infrastructure and high-performance computing.
They're looking for an experienced Analog/Mixed-Signal Design Engineer to develop high-speed wireline SerDes and optical transceiver technologies, from circuit architecture through to silicon validation and production.

The Role
  • Evaluate architectures for advanced high-speed SerDes and wireline transceivers.
  • Design and verify analog/mixed-signal CMOS circuits, including drivers, samplers, ADCs/DACs, PLLs and clocking circuits.
  • Collaborate with DSP and systems teams to optimise performance.
  • Evaluate and debug silicon, supporting products through to high-volume production.

What We're Looking For
  • MS or PhD in Electrical Engineering, Physics or a related field.
  • Strong high-speed analog CMOS circuit design experience.
  • Understanding of deep-submicron processes and wireline transceiver design.
  • Experience with SerDes, Cadence design tools and mixed-signal simulation.

Compensation & Benefits
  • $150,000–$300,000 base salary, depending on experience.
  • Performance bonus.
  • Comprehensive healthcare, 401(k), paid leave and additional benefits.

Please apply to find out more.

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