Reference:BH-2167
Sector:Electrical Engineering
Salary:$180,000 to $220,000 Per Annum
Benefits:Stock Options, Bonus & Benefits
Town/City:San Jose
Contract Type:Permanent
Active PIC Designer
Full-Time | Bay Area | $200K–$220K + Stock Options + Full Benefits
Innovate at the Core of Optical Interconnects!
We’re seeking an expert in silicon photonics to design and optimize high-speed active devices used in next-generation photonic integrated circuits. This role offers the chance to work across design, simulation, and testing, while influencing the future of scalable, high-bandwidth photonic systems.
You’ll own the design of high-performance components such as MZMs, ring modulators, and photodiodes, collaborating with fab teams, process engineers, and packaging experts.
What You’ll Do
What You Bring
What’s Offered
Full-Time | Bay Area | $200K–$220K + Stock Options + Full Benefits
Innovate at the Core of Optical Interconnects!
We’re seeking an expert in silicon photonics to design and optimize high-speed active devices used in next-generation photonic integrated circuits. This role offers the chance to work across design, simulation, and testing, while influencing the future of scalable, high-bandwidth photonic systems.
You’ll own the design of high-performance components such as MZMs, ring modulators, and photodiodes, collaborating with fab teams, process engineers, and packaging experts.
What You’ll Do
- Lead design and optimization of active photonic components including modulators and detectors.
- Perform full-cycle modeling, layout, and validation across multiple foundries.
- Work with test and characterization teams to analyze performance and refine designs.
- Contribute to documentation, IP development, and internal design standards.
- Mentor junior engineers and contribute to a collaborative technical culture.
What You Bring
- M.S. or Ph.D. in Photonics or related discipline, with 5+ years in silicon photonics design.
- Proven expertise in FDTD/MODE/DEVICE tools (Lumerical, Ansys, or Tidy3D).
- Experience with tapeouts across major SiPho foundries and understanding of process constraints.
- Strong Python/MATLAB skills for data analysis and yield improvement.
- Familiarity with co-design for ASIC interfaces and statistical modeling techniques.
What’s Offered
- $200K–$220K + Stock Options + Full Benefits
- Broad technical ownership and visibility
- Career growth in an elite, multidisciplinary team
- Opportunities to shape future product directions
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